Field of the Invention
The present invention relates to a layout method and layout program for a semiconductor integrated circuit device, and more particularly to a layout method and layout program for a semiconductor integrated circuit in which cell layout can be controlled with a high degree of flexibility.
A design process for a semiconductor integrated circuit comprises a logic design process for designing a logical circuit having a predetermined function, and a layout process for laying out macros, cells, and wires connecting the macros and cells on a chip using an automatic placement and routing program, on the basis of a net list, which is logical circuit information generated during the logic design process. With the increases in scale seen in recent years, a problem has arisen in that the number of steps required in the layout process has increased.
For example, first a floor planning step is performed to arrange an input/output circuit, a logical macro, a memory macro, a cell placement region, and so on within the chip, whereupon a plurality of cells is arranged within the cell placement region, and wires are generated and arranged between the cells. In this step, arrangement of the plurality of cells and arrangement of the connecting wires between the cells are performed automatically by a computer upon execution of an automatic placement and routing program tool (a layout program). Hence, when cell arrangement is not performed appropriately, the connecting wires therebetween may become longer, leading to situations in which the surface area efficiency of the connecting wires decreases, a portion of the connecting wires cannot be laid, and the power current supplied to the crowded plurality of cells is insufficient.
In a prior art proposal for preventing such problems, a cell placement prohibited region in which cell placement is prohibited, or a cell placement prohibited region in which cell placement is prohibited from a predetermined density upward, is set during the floor planning step to ensure that cells are not disposed in the positions and regions that cause such problems (see Japanese Unexamined Patent Application Publication H11-338892, Japanese Unexamined Patent Application Publication H10-4141, Japanese Unexamined Patent Application Publication H5-190813, Japanese Unexamined Patent Application Publication H5-152437, and so on, for example).
However, the cells arranged on the chip include not only normal cells constituting the logical circuit, but also timing adjustment cells for improving the signal delay characteristic of the connecting wires, capacitor cells for moderating voltage change in the power wires, and other cell types, and the regions in which cells can and cannot be disposed vary according to the cell type. Furthermore, the regions in which cell placement is to be restricted or prohibited differ in each step of the automatic layout process. As a result, operations to dispose a cell placement prohibited region on the chip and remove a disposed cell placement prohibited region must be performed repeatedly. Such repeated performance of these operations to dispose and remove cell placement prohibited regions is complicated and leads to an increase in the number of steps in the automatic layout process, and is therefore undesirable.